FIG. 1 shows two memory cells 102 and 104 of a typical ONO flash memory array 100, of which an ONO layer 108 is deposited on a substrate 106, polysilicons 110 and 112 and oxide layer 126 are formed on the ONO layer 108, a bit line 114 is implanted in the substrate 106 on the right of the polysilicon 110, a bit line 116 in the substrate 106 between the polysilicons 110 and 112, a bit line 118 in the substrate 106 on the left of the polysilicon 112, buried diffusion regions 120, 122 and 124 surrounding the bit lines 114, 116 and 118 respectively, a word line 128 is connected to the polysilicons 110 and 112, a channel 130 is formed between the buried diffusion regions 120 and 122, a channel 132 between the buried diffusion regions 122 and 124.
When the conventional ONO flash memory array 100 is programmed or erased the data 136 in the ONO layer 108 of the cell 104 by band-to-band technique, as shown in FIG. 1, the adjacent cell 102 will be programmed or erased and thereby the data 134 thereof 102 will be also disturbed. Similarly, a disturbance will be introduced when the data 136 of the cell 104 is read out.
To reduce the disturbances between adjacent memory cells of an ONO flash memory array, a bias voltage is additionally applied to the sources during the programming and erasing procedures. In the cell 102 of FIG. 1, for instance, −5V is supplied to the word line 128, +5V is supplied to the bit line 116, and +3V is additionally applied on the bit line 114. However, the introduction of additional bias will increase the power consumption and complexity of control circuit. Therefore, it is desired an ONO flash memory array capable of improving the disturbances between the adjacent memory cells thereof.